Programmable delay generator and cascaded interpolator

ABSTRACT

A programmable delay generator and a cascaded interpolator are provided. The programmable delay generator includes a first delay line and a second delay line, each having a respective plurality of stages of the same number. Each stage of the first line includes a respective delay buffer and has one signal input and one signal output. Each stage of the second line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first line and the second line are configured in parallel, are interconnected, and have a same signal propagation direction. Each delay step provided by each stage of the second line is equal to a difference between a delay through one stage of the first line and a delay through one stage of the second line.

GOVERNMENT RIGHTS

This invention was made with Government support under Contract No.:H98230-07-C-0409 awarded by the National Security Agency. The Governmenthas certain rights in this invention.

BACKGROUND

1. Technical Field

The present invention generally relates to the processing of clocksignals and, more particularly, to a programmable delay generator ofequal delay steps and a cascaded interpolator.

2. Description of the Related Art

Phase rotators are critical components of clock subsystems of moderndata processing and communications systems. Phase rotators are circuitsthat modify, in a highly precise and reproducible fashion, the phase ofclock signals within an unlimited phase range and therefore are capableof generating clock signals with programmable phase and frequencyoffsets. A very general approach to building phase rotators is to use atwo-stage circuit, where the first stage performs generation of a fixedset of clock phases that are uniformly distributed on a phase circleand/or selection of two adjacent phases from such a set, that isfollowed by the second stage that interpolates between the two selectedphases using a high-precision interpolator circuit. The most common wayto generate a set of coarse clock phases is to use a Delay Locked Loop(DLL) composed of the required number of identical delay stages, orobtain them using a divider of a higher clock frequency. Interpolationis conventionally done with current-mode logic (CML) mixers driven withcurrent-mode digital-to-analog converters (DACs). While highly linear,CML interpolators have poor compatibility with most recent circuitdesigns that are predominantly of the CMOS type, i.e., of the type thatemploy full (rail-to-rail) signal swing and cannot directly usereduced-swing CML clocks.

One can implement an interpolator that is CMOS-compatible by using acombination of two (or more) groups of dotted CMOS tri-state inverters,with each group receiving a common input signal and all groups havingone common output. The interpolation weights in this case are simply thenumbers of active inverters in each group (a tristate inverter can beeither fully on or off). However this method has lower linearity, andits nonlinearity increases with increases of the mutual delay of theclock phases, so it is generally limited to mutual delays of 45 degreesor less. Another disadvantage is the rigid relationship between theinterpolation accuracy in bits and the number of inverters present inthe circuit, the latter doubling with each extra bit of accuracy. Forexample, to create one output clock phase with 16 equidistantinterpolated states (4 bits of accuracy) one needs at least 32 tri-stateinverters for a single-ended output and 64 inverters for a dual-railoutput. An immediate consequence of such use of 2^n elements to achieven-bit accuracy is that such interpolator is natively controlled with athermometer code. However, a thermometer code uses N−1 bits to representN states, while binary code uses log 2(N) bits to represent N states.

The large number of coarse clock phases required by CMOS-typeinterpolators creates another important problem, namely skew introducedby the selection of the coarse phases from a large set, where askew-free selection of the coarse phases from a large set is desired.However, the skew-free selection of the coarse phases from a large setis challenging due to the significant size of phase-generation circuitryand the generally non-uniform topology of such a selector.

SUMMARY

According to an aspect of the present principles, there is provided aprogrammable delay generator of equal delay steps. The programmabledelay generator includes a first delay line and a second delay line. Thefirst delay line has a plurality of stages. Each of the plurality ofstages includes a respective delay buffer and has one signal input andone signal output. The second delay line has a plurality of stages equalin number to the plurality of stages of the first delay line. Each ofthe plurality of stages of the second delay line includes a respectiveselecting element and has two signal inputs, one select input forselecting one of the two signal inputs, and one signal output. The firstdelay line and the second delay line are configured in parallel withrespect to each other, are interconnected, and have a same signalpropagation direction. Each of the delay steps provided by each of theplurality of stages of the second delay line is equal to a differencebetween a delay through one of the plurality of stages of the firstdelay line and a delay through one of the plurality of stages of thesecond delay line.

According to another aspect of the present principles, there is provideda method for programmable delay generation of equal delay steps. Themethod includes forming a first delay line having a plurality of stages.Each of the plurality of stages includes a respective delay buffer andhaving one signal input and one signal output. The method furtherincludes forming a second delay line having a plurality of stages equalin number to the plurality of stages of the first delay line. Each ofthe plurality of stages of the second delay line includes a respectiveselecting element and has two signal inputs, one select input forselecting one of the two signal inputs, and one signal output. The firstdelay line and the second delay line are configured in parallel withrespect to each other, are interconnected, and have a same signalpropagation direction. Each of the delay steps provided by each of theplurality of stages of the second delay line is equal to a differencebetween a delay through one of the plurality of stages of the firstdelay line and a delay through one of the plurality of stages of thesecond delay line.

According to yet another aspect of the present principles, there isprovided a cascaded interpolator. The cascaded interpolator includes aplurality of interpolator stages. Each of the plurality of interpolatorstages has two signal inputs and two signal outputs, and is configuredto receive two input signals having two different phases and to generatetherefrom two output signals that have a phase separation equal to afraction of a phase separation of the two input signals. The cascadedinterpolator further includes a phase converter connected to a laststage of the plurality of single-bit interpolator stages. The phaseconverter is configured to convert the two output signals into a singlefinal output signal of a given phase.

According to still another aspect of the present principles, there isprovided a method for cascaded interpolation. The method includesforming a plurality of interpolator stages. Each of the plurality ofinterpolator stages has two signal inputs and two signal outputs, and isconfigured to receive two input signals having two different phases andto generate therefrom two output signals that have a phase separationequal to a fraction of a phase separation of the two input signals. Themethod further includes forming a phase converter connected to a laststage of the plurality of single-bit interpolator stages. The phaseconverter is configured to convert the two output signals into a singlefinal output signal of a given phase.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIGS. 1A and 1B are diagrams collectively showing a two-stage phaserotator 100, in accordance with the prior art;

FIG. 2 is a diagram showing an all-CMOS phase rotator 200 with 64states, in accordance with an embodiment of the present principles;

FIG. 3 is a diagram further showing a coarse stage 298 of the all-CMOSphase rotator 200 of FIG. 2, in accordance with an embodiment of thepresent principles;

FIG. 4 is a diagram further showing a fine stage 299 of the all-CMOSphase rotator 200 of FIG. 2, in accordance with an embodiment of thepresent principles;

FIG. 5 is a diagram showing a 3 bit version of a fine rotator 500, inaccordance with an embodiment of the present principles;

FIG. 6 is a diagram showing states 600 of the 3 bit fine rotator 500 ofFIG. 5, in accordance with an embodiment of the present principles;

FIG. 7 is a diagram showing a dual-rail CMOS buffer stage 700 with slewrate control, in accordance with an embodiment of the presentprinciples;

FIG. 8 is a diagram showing a duty cycle adjusting dual-rail buffer 800with slew rate control, in accordance with an embodiment of the presentprinciples;

FIG. 9 is a diagram showing an edge-aligned dual-rail buffer 900 withslew rate control, in accordance with an embodiment of the presentprinciples;

FIG. 10 is a diagram showing a 1:1 interpolator 1000, in accordance withan embodiment of the present principles;

FIG. 11 is a diagram showing a 2:1 dual-rail multiplexer 1100 with aslew rate control, in accordance with an embodiment of the presentprinciples;

FIG. 12 is a diagram showing a modified 2:1 dual-rail multiplexer 1200with feed-through cancelation, in accordance with an embodiment of thepresent principles;

FIG. 13 is a diagram showing a polarity control (XOR) dual-rail circuit1300 with an additional “disable” state, in accordance with anembodiment of the present principles;

FIG. 14 is a diagram showing an interpolator 1400, in accordance with anembodiment of the present principles;

FIG. 15 is a diagram showing a method 1500 for programmable delaygeneration of equal delay steps, in accordance with an embodiment of thepresent principles; and

FIG. 16 is a diagram showing a method 1600 for cascaded interpolation,in accordance with an embodiment of the present principles.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

As noted above, the present principles are directed to programmabledelay generator of equal delay steps and a cascaded interpolator. Boththe programmable delay generator and the binary encoded cascadedinterpolator are implemented as all-CMOS. As used herein, “all-CMOS”refers to a circuit where signals in all points in the circuit havefull, rail-to-rail swing.

With respect to one or more embodiments, the present principles aim tocreate an all-CMOS phase rotator, or elements (e.g., the programmabledelay generator and the binary encoded cascaded interpolator) that arecapable of being in such a phase rotator, using a novel topology thatallows the rotator to merge phase generation and phase selectioncircuitry into a uniform array of delay stages and switching elementsthat achieves equidistant separation of the selected phase positions byconstruction. Moreover, a new topology of the CMOS-type interpolator isintroduced that includes a cascade of identical 1-bit sections forsignificant hardware savings in contrast to conventionalthermometer-encoded CMOS interpolators.

Thus, the present principles are directed to an original architecturefor an all-CMOS phase rotator, where the architecture can be consideredto include two independent components, where each of these componentsare novel over the prior art. The first component involves the efficientgeneration of one pair of adjacent clock phases out of a relativelylarge set of equidistant clock phases (as opposed to a more conventionalway to first generate a full set and then to proceed to select just twophases out of that full set). This generation is based on using auniform array of delay and switching elements that utilizes verniertopology. As used herein, a vernier topology refers to and/or isotherwise directed to, an array where the delay introduced by such arraychanges in increments equal to a difference between two schematicdelays. That is, the delay changes in increments equal to a differencebetween a signal propagation delay through one stage of a first (main)delay line, and a signal propagation delay through one stage of a second(merging) delay line. The second architecture component involves the useof a multiple stage interpolator that interpolates between the incomingpair of relatively close clock phases using a cascade of identicalsingle-bit sections, each having two inputs and two outputs and onecontrol bit that adds one bit of accuracy to the overall interpolationprocess. More specifically, each interpolation stage includes a 2:1 MUXand a fixed 1:1 mixer (interpolator). The 2:1 MUX selects one of the twoincoming phases as the first output. The fixed 1:1 mixer (interpolator)generates the second output. The last stage in the cascade is terminatedwith a single 1:1 mixer to produce the final single rotator output. Theuse of the preceding architecture advantageously results in thesituations where, depending on the control bit value in each section,its output pair of phases takes one of two possible configurations,while the spacing between these two phases is reduced by a factor oftwo.

As will be appreciated by one skilled in the art, aspects of the presentinvention may be embodied as a system, method or computer programproduct. Accordingly, aspects of the present invention may take the formof an entirely hardware embodiment, an entirely software embodiment(including firmware, resident software, micro-code, etc.) or anembodiment combining software and hardware aspects that may allgenerally be referred to herein as a “circuit,” “module” or “system.”Furthermore, aspects of the present invention may take the form of acomputer program product embodied in one or more computer readablemedium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may beutilized. The computer readable medium may be a computer readable signalmedium or a computer readable storage medium. A computer readablestorage medium may be, for example, but not limited to, an electronic,magnetic, optical, electromagnetic, infrared, or semiconductor system,apparatus, or device, or any suitable combination of the foregoing. Morespecific examples (a non-exhaustive list) of the computer readablestorage medium would include the following: an electrical connectionhaving one or more wires, a portable computer diskette, a hard disk, arandom access memory (RAM), a read-only memory (ROM), an erasableprogrammable read-only memory (EPROM or Flash memory), an optical fiber,a portable compact disc read-only memory (CD-ROM), an optical storagedevice, a magnetic storage device, or any suitable combination of theforegoing. In the context of this document, a computer readable storagemedium may be any tangible medium that can contain, or store a programfor use by or in connection with an instruction execution system,apparatus, or device.

A computer readable signal medium may include a propagated data signalwith computer readable program code embodied therein, for example, inbaseband or as part of a carrier wave. Such a propagated signal may takeany of a variety of forms, including, but not limited to,electro-magnetic, optical, or any suitable combination thereof. Acomputer readable signal medium may be any computer readable medium thatis not a computer readable storage medium and that can communicate,propagate, or transport a program for use by or in connection with aninstruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmittedusing any appropriate medium, including but not limited to wireless,wireline, optical fiber cable, RF, etc., or any suitable combination ofthe foregoing.

Computer program code for carrying out operations for aspects of thepresent invention may be written in any combination of one or moreprogramming languages, including an object oriented programming languagesuch as Java, Smalltalk, C++ or the like and conventional proceduralprogramming languages, such as the “C” programming language or similarprogramming languages. The program code may execute entirely on theuser's computer, partly on the user's computer, as a stand-alonesoftware package, partly on the user's computer and partly on a remotecomputer or entirely on the remote computer or server. In the latterscenario, the remote computer may be connected to the user's computerthrough any type of network, including a local area network (LAN) or awide area network (WAN), or the connection may be made to an externalcomputer (for example, through the Internet using an Internet ServiceProvider).

Aspects of the present invention are described below with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems) and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer program instructions. These computer program instructions maybe provided to a processor of a general purpose computer, specialpurpose computer, or other programmable data processing apparatus toproduce a machine, such that the instructions, which execute via theprocessor of the computer or other programmable data processingapparatus, create means for implementing the functions/acts specified inthe flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computerreadable medium that can direct a computer, other programmable dataprocessing apparatus, or other devices to function in a particularmanner, such that the instructions stored in the computer readablemedium produce an article of manufacture including instructions whichimplement the function/act specified in the flowchart and/or blockdiagram block or blocks.

The computer program instructions may also be loaded onto a computer,other programmable data processing apparatus, or other devices to causea series of operational steps to be performed on the computer, otherprogrammable apparatus or other devices to produce a computerimplemented process such that the instructions which execute on thecomputer or other programmable apparatus provide processes forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof code, which comprises one or more executable instructions forimplementing the specified logical function(s). It should also be notedthat, in some alternative implementations, the functions noted in theblock may occur out of the order noted in the figures. For example, twoblocks shown in succession may, in fact, be executed substantiallyconcurrently, or the blocks may sometimes be executed in the reverseorder, depending upon the functionality involved. It will also be notedthat each block of the block diagrams and/or flowchart illustration, andcombinations of blocks in the block diagrams and/or flowchartillustration, can be implemented by special purpose hardware-basedsystems that perform the specified functions or acts, or combinations ofspecial purpose hardware and computer instructions.

The present invention aims at advancing the architecture of phaserotators that use full-swing (rail-to-rail) signaling, also known asCMOS signaling, for reduction of circuit power and area compared tocircuits that utilize the more traditional signaling for analogcircuits, namely reduced-swing differential signaling which is alsoknown as CML signaling. Regardless of the type of the signaling, thevast majority of phase rotator architectures can be described as atwo-stage circuit that employs a coarse stage and a fine stage that itis convenient to illustrate using the specific example in FIGS. 1A and1B.

FIGS. 1A and 1B collectively show a two-stage phase rotator 100, inaccordance with the prior art. In particular, FIG. 1A shows aDelay-Locked Loop (DLL) 103 and multiplexers 120 of the phase rotator100, wherein the DLL 103 is for coarse phase generation, and themultiplexers 120 are for coarse phase selection. The DLL 103 includes acore DLL 101 and a peripheral DLL 102. FIG. 1B shows a CML interpolator150 of the phase rotator 100. The CML interpolator 150 is for fine phasegeneration.

The DLL 103 is composed of N=6 identical delay stages/elements 111 withcontrollable delay that is adjusted by the feedback loop 104 to yield anoverall phase delay of 180 degrees. Since the delay stages/elements 111are nominally identical, this phase delay is uniformly distributedbetween these N elements 111, yielding 180/N=30 degrees of phase delayper each delay element 111. The delay elements 111 are implemented asCML circuits using differential, reduced swing signaling and thereforethey automatically provide another 6 complementary phases with a 180degree shift thus yielding a complete set of 2N=12 clock phases that areuniformly distributed on a phase circle.

The next step within the coarse stage of the rotator 100 shown in FIG.1A is the selection of two adjacent phases from a full 2N-phase set.This is done by dividing the 6 taps 112 (each having a buffer 113) ofthe DLL 110 into two groups, even and odd (3 taps each) and passing eachgroup through an individual 3:1 multiplexer 120 followed by a polarityselector 125. The polarity selector 125 is shown in FIG. 1A as a 2:1multiplexer driven by two opposite polarities of the signal. The selectcontrols of all these multiplexers 120, 125 are operated in such waythat the two output clock phases, an even and an odd clock phase, arealways located next to each other on a phase circle (further referred toas “adjacent coarse phases”). This completes the description of coarsephase selection.

The two adjacent coarse phases, an even and an odd, are then applied tothe fine stage which is implemented using a CML interpolator 150 shownin detail in FIG. 1B. The CML interpolator 150 is realized as a summingcircuit that adds together the differential currents from twodifferential pairs 161, 162 driven by the two coarse clock phases andapplies them to a common differential load 170. The amplitudes of thesetwo currents, i.e. their respective interpolation weights, are set usingtwo current DACs 181, 182. Each of the two current DACs 181, 182includes 16 identical unit sections driven by thermometer code.

The interpolation accuracy of CML interpolators similar to that shown inFIG. 1B is sufficiently high to accurately interpolate between clockphases with phase separation as large as 90 degrees, therefore amajority of CML rotators operate with a set of just four coarse phases,i.e. just two differential clock signals, commonly referred to asIn-phase (I) and Quadrature (Q) clock phases, that can be obtained inmany cases without use of delay elements, e.g. by using a 2:1 divider ofa single differential clock signal at double frequency.

In contrast to CML interpolators, interpolators using CMOS signalinghave generally worse linearity and therefore require a larger number ofcoarse phases with respectively finer spacing to operate adequately(usually 8 phases or more). As a consequence, in the design of phaserotators using CMOS signaling, larger emphasis is put on the precisionof the coarse stage that applies to both coarse phase generation and thesubsequent selection for the final coarse output.

The root issue of potential inaccuracies in the output coarse phases(obtained via the aforementioned two-step process involving thegeneration of a complete phase set followed by the selection of just twoof the phases in the set) is that the resulting structure is redundant(most phases are not used at any given moment) and the phase collectionnetwork that brings the phases to the phase selection devices oftenlacks symmetry and/or uniformity. To address this issue, the presentprinciples introduce a new topology for coarse phase generation that isfree from these deficiencies. More specifically, the new presentprinciples merge delay generation elements and switching (selection)elements in a uniform array of multiple stages that can directlygenerate the two output coarse phases (belonging to a large set ofequidistant phases) without generating the ones that are not needed.

FIG. 2 shows an all-CMOS phase rotator 200 with 64 states, in accordancewith an embodiment of the present principles. The all-CMOS phase rotator200 includes a coarse stage 298 and a fine stage 299. FIG. 3 furthershows the coarse stage 298 of the all-CMOS phase rotator 200 of FIG. 2in accordance with an embodiment of the present principles. FIG. 4further shows the fine stage 299 of the all-CMOS phase rotator 200 ofFIG. 2 in accordance with an embodiment of the present principles.

The all-CMOS phase rotator 200 includes a coarse phasegenerator/selector 210 corresponding to the coarse stage 298 and a finephase rotator stage 250 corresponding to the fine stage 299. The finephase rotator stage 250 includes a fine phase one-bit cascadableinterpolation section 251 and a termination stage 260. Hence, theall-CMOS phase rotator 200 of FIG. 2 has 64 states using 32 coarsephases and a single one-bit interpolation stage.

In the embodiment of FIG. 3, the coarse phase generator/selector 210 isfor selecting 2 coarse phases (Even and Odd) out of a set of 32equidistant phases that uses vernier topology. In the embodiment of FIG.4, the fine phase rotator stage 250 includes the one-bit cascadableinterpolation section 251 with two input phases and two output phases,and further includes the termination stage 260 that converts two finalphases into a single output phase (denoted “final output”).

Similar to the rotator 100 of FIG. 1, the incoming clock (ROT CLK IN) inthe coarse stage 298 is first applied to a tapped delay line 211 thatincludes identical delay stages, with even and odd taps forming twoseparate groups (placed above and below the tapped delay line in FIGS. 2and 3). In contrast to FIG. 1, where all M taps of a given group werefirst applied to a M:1 multiplexer and then to a polarity switch toobtain the final output coarse phase (even or odd), the new architectureas shown in FIG. 2 employs a uniform distributed structure made of delayelements 277 and 2:1 multiplexers 278 which form a switched delay line212 as well delay elements 276 which form a main tapped delay line 211to perform the same function. More specifically, each tap off of themain tapped delay line 211 is first applied to a polarity switch 213(also labeled XOR, since that is the logical operation of a polarityswap) and then the tap is merged into a second delay line 212 (furtherreferred to as “merging delay line”) that has the same direction ofsignal propagation as the main tapped delay line 211, but is made ofidentical stages that include one delay element 277 and one 2:1multiplexer 278 that receives at its second input the polarity-adjustedsignal from a respective tap (even or odd) of the main tapped delay line211. Only one of the taps in each group (even and odd) is active,meaning that the input clock signal (ROT CLK IN) first reaches theselected tap along the main tapped delay line 211, then propagatesthrough the polarity selector XOR 213 and receives the desired polarity,and then propagates along the second delay line 212 in the samedirection until it emerges at its respective output terminal (even orodd).

The two main distinctive features of the new architecture of the coarserotator stage 298 shown in FIGS. 2 and 3 are first, uniformity, i.e. thetopology of the structure does not change with the total number of taps(it remains a linear array of identical sections that receives an inputclock signal on its left side and generates two desired coarse phases onthe right side), and second, it employs a vernier topology, meaning thatthe change in delay of the output coarse phase in a given group when theactive (selected) tap shifts by one position, is equal to a differencein delays along the main tapped delay line 211 (delay of two bufferelements) and the delay along the second (merging) delay line 212 (delayof one buffer and one 2:1 multiplexer). This difference in the twodelays can be made sufficiently small to accommodate a very large numberof coarse phases (like 32 in FIGS. 2 and 3) even at high clockfrequencies, where the propagation delay of the main tapped delay line211 would be significantly larger than 180 degrees. Compare that to therotator 100 in FIG. 1 that needs the total delay of its tapped delayline to be 180 degrees leading to a limit on its maximum clock speed,since clock phase delay in a delay line with a fixed delay isproportional to the clock frequency. In a case of a vernier delaystructure such as that shown in FIGS. 2 and 3, one needs to set only thedifference between the two delays to 180 degrees, while each of the twodelays can be larger than 180 degrees. For example, one can set thedelay of the main tapped delay line 211 to 360 degrees and the delay ofthe merging delay line 212 to 180 degrees giving the desired differenceof 180 degrees, as shown in FIG. 3.

The second independent innovation of the new rotator architecture shownin FIG. 2 is the use of a hardware-saving interpolator in the rotatorfine stage 299 with a resolution of n bits that replaces a singlethermometer-encoded interpolator stage using 2^(n) identical unitelements with a cascade of n identical one-bit sections, plus theadditional termination stage 260. The fine rotator stage 299 shown inFIG. 4 is for the case n=1 which includes just one single-bit cascadableinterpolator 251 that has two clock inputs and two clock outputs. Thiscascadable one bit interpolator 251 works as follows: its first output(labeled as “E” for even) simply repeats one of the two input signalsvia use of a 2:1 multiplexer controlled with a single-bit select signal(labeled “1b control”). The second output (labeled as “O” for odd) isobtained by 1:1 interpolation between the two inputs, therefore itsoutput phase takes position at the mid-point between the two possiblephase positions of the first output. The termination stage 260 convertsthe two-phase output of the last interpolation section in the cascade toa single final output. The termination stage 260 is simply a 1:1interpolator, so it places the final output of the fine rotator stage atmid-point between the two output phases of the last single-bitinterpolation stage.

In order to explain the principles of clock phase transformations asthey propagate through the cascade of single-bit interpolators and thefinal termination stage 260, let us consider a 3 bit fine phase rotatorstage. FIG. 5 shows a 3 bit version of a fine rotator 500, in accordancewith an embodiment of the present principles. The fine rotator 500includes three cascaded single-bit sections (with “stage 0” denoted bythe reference numeral 510, “stage 1” denoted by the reference numeral511, and “stage 2” denoted by the reference numeral 512) and atermination stage 560 that converts two final phases into a singleoutput phase. FIG. 6 shows states 600 of the 3 bit fine rotator 500 ofFIG. 5, in accordance with an embodiment of the present principles. The3 bit fine rotator 500 is natively controlled by Gray code and eachsingle-bit stage doubles the number of phase states and reduces phaseseparation in half.

FIGS. 5 and 6 show that the resolution of the rotator 500 doubles witheach single-bit interpolation stage, and that the number of phase statesavailable at the outputs of each single-bit interpolation stage isdoubled compared to its inputs. More specifically, the available outputphase states always include all the available input states (those arerouted to the even output) plus they include an equal amount of newinterpolated states located at mid-points between the input states(those are routed to the odd output). At the same time each single-bitstage reduces the phase separation in half so the resolution of the finerotator stage doubles with each additional interpolation stage. This isin contrast to conventional interpolation architectures where doublingthe interpolation resolution is associated with doubling the hardware.FIG. 6 also illustrates how the one-bit controls of its three single-bitsections 510, 511, and 512 are switched when its output is continuouslyincrementing in phase and shows that the control code of such finerotator 500 is a Gray code that changes its individual bits one at atime when transitioning between adjacent states, thus minimizing thepotential for the development of glitches at the output during changesin rotator position.

This completes the architectural description of the new phase rotator,however on the circuit level (not shown in FIGS. 2-5) the phase rotatordoes use several innovations that are described herein below and dealpredominantly with the issues of designing slew-rate-limited CMOSbuffers for the purpose of delay generation, interpolation and dutycycle adjustment. A related topic is the implementation of“feedthrough-free” multiplexers that are required to implement accuratesingle-bit interpolators with CMOS circuits. Finally, the actualimplementation of the present principles in hardware employs so-called“glitchless switching” techniques that apply both to the control of thecoarse phase selector as well as the cascaded fine interpolatorcontrolled with Gray code. In both cases the suggested solution forglitchless switching involves operating the 2:1 multiplexers as 1:1interpolators during code changes, i.e. using two instances of a 2:1multiplexer in parallel and applying the code change to one copy beforethe other.

We will now discuss an implementation of the buffer delay stages of therotator. FIG. 7 shows a dual-rail CMOS buffer stage 700 with slew ratecontrol, in accordance with an embodiment of the present principles. Thedual-rail CMOS buffer stage 700 includes two inverters 711, 712 withshared supply terminals which in turn are driven by two current-limitingtransistors, a PFET 720 for a pull-up path and an NFET 730 for apull-down path. Both these transistors 720, 730 are configured ascontrollable current sources that drive the capacitive load at theoutput nodes of the inverters 711, 712 up or down, and therefore theyoperate as limiters of the maximum slew rate for the rising and fallingedges of the inverter outputs respectively. Accordingly, by modifyingthese currents (via controlling the gate voltages of these transistors)one achieves independent control of the propagation delay for the risingand falling edges respectively. Normally the pull-up and pull-downcurrents are kept nominally equal (and hence the rise and fall slewrates of the buffer outputs and their respective delays), but in certainmore complex circuits they can be controlled independently, for example,for adjusting the duty cycle of the waveforms.

FIG. 8 shows a duty cycle adjusting dual-rail buffer 800 with slew ratecontrol, in accordance with an embodiment of the present principles. Thebuffer 800 is similar to the buffer 700, but in contrast supplies eachinverter 811, 812 with a separate pair of pull-up 721, 722 and pull-downdevices 731, 732 with independent control. That is, inverter 811 isprovided with its own pull-up transistor 721 and pull-down transistor731, and inverter 812 is provided with its own pull-up transistor 722and pull-down transistor 732. For example, in order to increase the dutycycle of a dual-rail clock waveform with aligned edges, i.e.simultaneously increase the duty cycle of its true signal and decreasethe duty cycle of the complementary signal, one increases the pull-upcurrent and decreases the pull-down current of the inverter generatingthe true output and at the same time deceases the pull-up current andincreases the pull-down current of the inverter generating thecomplementary output.

An important observation is that the two inverters of the regulardual-rail buffer in FIG. 7 can easily share a single pair of currentsources due to the fact that they process complementary clock signals,so when one inverter generates a rising edge and hence uses a pull-upPFET device, the other inverter is generating a falling edge on thecomplementary output and therefore uses the pull-down NFET device. Thismode of operation eliminates the situation when both inverters need touse the same current source at the same time and allows for sharing asingle set of current sources which yields a significant circuit areasavings due to the fact that the current sources usually dominate thelayout area.

FIG. 9 shows an edge-aligned dual-rail buffer 900 with slew ratecontrol, in accordance with an embodiment of the present principles.Thus, the buffer 900 provides an enhanced topology of a dual-railslew-rate-controlled buffer that adds an edge alignment function. Incomparison to the buffer 700 of FIG. 7, buffer 900 includes twoadditional small cross-coupled inverters 741, 742 that correct smalltiming mismatches between rising and falling edges of the two clockwaveforms on the complementary outputs of the circuit, thus preventingmisalignment error accumulation in a long chain of buffers. This buffertopology is used in all dual-rail buffers shown in FIG. 2.

The basic buffer topology in FIG. 7 can be also used as a building blockfor more complex circuits used in accordance with the teaching of thepresent principles, specifically, 1:1 interpolators and 2:1multiplexers. For example, FIG. 10 shows a 1:1 interpolator 1000, inaccordance with an embodiment of the present principles. Theinterpolator 1000 can be built from two instances of the dual-railbuffer 700 shown in FIG. 7 that have shared outputs but independentinputs. Hence, inverters 1013 are similar to inverters 711. If thedifference in clock signal phases applied to these two independentinputs is small, this circuit works as a precise 1:1 interpolator, i.e.it generates the average between the respective outputs of the twounconnected buffers. This happens because when the outputs of twoindependent buffers with limited pull-up and pull-down currents areconnected, the shared output load is initially driven only by thecurrent sources of the buffer that receives the early clock phase, i.e.at ½ of maximum slew rate, and then upon arrival of the late clock phasethe slew rate doubles to its full maximum value, thus generating theexpected 1:1 interpolated output.

The reason for the input phases to be relatively close is to avoid acrow-bar condition between the two buffers. Such condition develops whenthe mutual delay between the two input phases is sufficiently large tobecome a significant portion of the output transition time. Considerthat before the early clock phase transition there are no currents inthe circuit, since all active pull-up and pull-down current sources(i.e. those connected to the outputs via inverters) have reached zeroheadroom. The inverters receiving the late phase will retain their zerocurrents as long as the change in the circuit outputs caused by theearly-phase inverters action is small to keep the headroom of itscurrent sources in the late-phase ones sufficiently low to prevent themfrom applying an opposing current to the outputs. This is easilyachieved in the new architecture due to its use of the vernier principlethat allows one to have relatively slow slew rates in combination withsmall phase separation that must be a small fraction of the total outputtransition time, which has a maximum value of one half of the clockperiod.

FIG. 11 shows a 2:1 dual-rail multiplexer 1100 with a slew rate control,in accordance with an embodiment of the present principles. Themultiplexer 1100 is similar to the buffer 700 of FIG. 7 in the sensethat it is driven by just one pair of current-limiting transistors 720,730, but uses four inverters 1111 that receive two dual-rail clocksignals and these inverters 1111 are tri-state inverters in contrast toplain inverters 711, 712 in FIG. 7. The extra switches (2 each of ST andSC, as depicted in FIG. 11) within the tri-state inverters that connectand disconnect them to supply rails are configured to activate theinverters that process only one of the selected dual-rail clock phase.In other words, at any given moment such multiplexer circuit isconfigured as a simple buffer shown in FIG. 7 and therefore can beoperated from a single set of current sources.

The primary reason to use current-limiting devices in the multiplexers278 used in the rotator 200 shown in FIG. 2 despite the fact that therotator can operate without the current-limiting devices (i.e., with themultiplexers 278 connected directly to the power supply rails), is toreduce the dependence of propagation delay through the multiplexers 278on changes in the power supply voltage. This can be achieved, forexample, by using a feedback loop (not shown in FIGS. 2, 3) thatmodifies the control voltage of the current sources to counter-act theeffect of supply voltage variations for maximum suppression of changesin propagation delay.

An important shortcoming of the multiplexer 1100 shown in FIG. 11 is theeffect of capacitive feed-through that can be explained as follows.Consider the disabled pair of tri-state inverters that isolate themultiplexer dual-rail output from the de-selected dual-rail clock input.Despite these inverters being powered off, i.e. disconnected from thesupplies, there is still significant capacitance between their inputsand outputs that results in transients at the inputs propagating to theoutput (an effect known as “capacitive feed-through”) and thuspotentially corrupting the exact timing of the rising and falling edgesof the multiplexer output leading to significant degradation of therotator performance.

There are two independent ways to cancel the effect of such capacitivefeed-through, both of which are used in the invention. The first way isto add a complete set of four dummy (permanently disabled) tri-stateinverters 1211 to the circuit shown in FIG. 11 that results in a circuitshown in FIG. 12 that has 8 tri-state inverters, in two groups of 4,each group sharing a common output. That is, FIG. 12 shows a modified2:1 dual-rail multiplexer 1200 with feed-through cancellation, inaccordance with an embodiment of the present principles. Each pair ofdummy inverters within one group (of the groups 1213 and 1214) receivesthe clock signals of opposite phase in respect to the regular ones,i.e., use input signals that are already available within the circuit.With such arrangement when a given clock input is disabled, both of itspolarities will couple symmetrically to the multiplexer outputs thuscanceling each other. The overhead in circuit area of this approach isrelatively low since the circuit area is typically dominated by thecurrent sources which did not change, since the modified circuit with is8 tri-state inverters still uses a single set of current sources. Itsmain disadvantage is that the additional disabled tristate invertersincrease the load at the multiplexer output and therefore increase itsdelay and/or power.

There is an alternative second way to eliminate the effect of capacitivefeed-through by forcing the de-selected clock input to some fixed valuethat can be achieved by appropriately controlling the circuit thatgenerates it. This second approach essentially shifts the problem fromthe original multiplexer circuit in FIG. 11 (that is unchanged) tocontrolling the source of input lock signal, so if one can easily setits output to a fixed value, the second approach is preferable to thefirst one.

In accordance with the present principles, the first approach (extradummy tri-state inverters 1211) is used in the fine rotator stage 299,i.e. within the singe-bit interpolators 251. The coarse phase generationstage 298, in contrast, is sensitive to additional increases in delayand/or power, and therefore it employs the second approach.

Let us explain how one can implement the second approach in the coarserotator stage 298, where the multiplexers 278 are driven by polaritycontrol circuits (XOR) 213 on one input and by delay buffers 277 of themerging delay line 212 on the other input. Feed-through cancellation inthis structure is achieved primarily by de-activating (i.e. forcing to afixed output value) the majority of XOR circuits 213 that connect theunused taps of the main tapped delay line 211 to the multiplexers 278 ofthe merging delay line 212. FIG. 13 shows a polarity control (XOR)dual-rail circuit 1300 with an additional “disable” state, in accordancewith an embodiment of the present principles. The XOR circuit 1300 isobtained from the 2:1 multiplexer 1100 shown in FIG. 11 by connectingits two inputs to the same dual-rail clock signal, but in oppositepolarity. De-activation of a XOR circuit 1300 is achieved as follows.The tri-state inverters 1311 of this multiplexer are controlled with twologic signals S1, S2 that are nominally complementary, i.e. take either“01” or “10” values that represent selection of the inverting ornon-inverting input respectively. However if one uses two equal values,e.g. “11”, this polarity control circuit will force both outputs to low,i.e. to a constant value, and hence will prevent them from creating anyfeed-through effect in the 2:1 multiplexer circuit driven by it.

Let us now consider an independent topic of glitchless switching.Generally a glitch within the coarse phase generation stage 298 occurswhen a certain multiplexer in the clock path switches between two clockphases that are significantly far apart (e.g. have opposite polarity)and therefore can assume significantly different values at the moment ofswitching. A particularly dangerous condition occurs at the so-called“stitching region” where the phase at one end of the delay linestructure is replaced with the phase at the other end (with change inpolarity to compensate for 180 degrees of phase delay along the delayline).

In order to guarantee that phase switching within the coarse phasegenerator is glitch-free, the following measures are taken: first, XORcells of all taps except the main tap and two adjacent to it are kept ina disabled state, as explained above. (The main tap is the tap throughwhich the clock is routed on its path from the tapped delay line to theeven and odd merging delay lines.) In order for a tap to change polarityit must be de-activated first. Second, the 2:1 multiplexers 278 of themerging delay line 212 are configured so that the multiplexer driven bythe main active tap and all multiplexers to the left of it are in the“merging” position (i.e. they accept the signal from their respectivetaps and disregard the signal from their preceding buffers in themerging delay line), while all multiplexers to the right of it are setin a “propagation” state, i.e. they receive the signal from thepreceding buffer in the merging delay line and disregard the tap signalfrom their respective XOR cell input. The only exception is the leftmostmultiplexer (tap 0) that has no left neighbor and hence is permanentlywired in the “merge” position. The overall goal of such arrangement isto be always prepared for a tap switching (translation) process by oneposition in either direction, in a way that such translation of the tapposition could be accomplished by switching just one 2:1 multiplexer inthe merge delay line 212. More specifically, a move to the left would beaccomplished by reversing the select state of the multiplexer of themain tap from merging to propagating, while moving the active tapposition by one step to the right is achieved by reversing the selectstate of the multiplexer to the right from the main one, frompropagating to merging.

Besides those primary switching events that directly alter the clockpropagation path, one would also need to switch the select state of theperipheral taps to restore the same active tap configuration that istranslated by one position to the left or to the right. Such translationsimply means de-activation of XOR cell of one tap and activation of XORcell of another to form a new group of three active taps. These XOR cellswitching events however have no direct effect on the main clockpropagation path and hence their timing is not critical.

A special case that is handled slightly differently arises near thestitching boundary that involves the taps on the two opposite sides ofthe coarse delay generator, since those edge positions have only oneneighbor tap. In order to make moves of active tap position across thestitching boundary identical to regular ones, the structure uses aredundant tap (numbered 8) that replicates the first tap (numbered 0) ina sense that the two are set exactly 180 degrees apart in phase and arealways activated in opposite polarity states, so the clock paths routedthrough them would result in an identical output (selection of which oneis actually routed to the output is determined by the select state ofthe multiplexer associated with the redundant, 8^(th) tap). With sucharrangement when both tap 0 and tap 8 are active, one uses tap 1 as the“right” extra tap, and tap 7 as “left” extra tap of the “three tapsactive” combination and hence the general rule described in thepreceding paragraph for regular (non-boundary) taps seamlessly appliesto the redundant boundary tap pair 0,8.

In order to further enhance the glitch suppression capabilities of thecoarse phase generator all multiplexers within the merge delay lines areimplemented as 1:1 interpolators, i.e. they are made of two identicalmultiplexer 1100 instances shown in FIG. 11 that share the inputs andoutputs, but have independent selection controls. The two sets ofcontrols in turn are obtained from a single set by using two mutuallydelayed copies of it, so the “early” set simply copies the originalcontrol set, while the “late” set is delayed by one period of a clocksignal that is used to operate the rotator controls (generally slowerthan the main rotator clock). Such arrangement means that during thecontrol clock period when early set has already changed, but the lateset still holds the original value, the multiplexer operates as 1:1interpolator similar to interpolator 1000 shown in FIG. 10. As it hasbeen described in the previous section which introduced the concept ofthree active taps, the clock phases that are applied to the multiplexersare already sufficiently close in phase, so their interpolation productforms a properly-shaped new clock phase that has an intermediate phasevalue, so no glitching occurs on the clock waveform even if it goesthrough a transition at the moment when the multiplexer switching takesplace. Separation of the switching into two intermediate events (earlyand late) also simplifies the management of XOR cell activations anddeactivations during tap transition by one position. Specifically, allnew XOR cell activations take place immediately on early event arrival,thus bringing the total number of active taps temporarily from three tofour, while all de-activations take place one control clock periodlater, thus bringing the number of active taps back to three, but in anupdated configuration.

An additional benefit of using interpolating multiplexers takes place inthe redundant (8^(th)) tap which during activation of this tap (as main,center tap) is allowed to assume either one of its two select states,i.e. choose either routing the clock signal through tap 0 (the leftmost)or through tap 8 (the rightmost). In practice, the best position tochoose in this case is of constant (non-transitory) 1:1 interpolationbetween these two paths since it minimizes the error arising from thefinite accuracy of setting the delay line to a phase delay of 180degrees (commonly referred to as “stitching error”). The latter positionis easily achievable with the interpolating multiplexer by applying thecontrols accordingly.

The interpolating multiplexer enables glitchless switching not only inthe coarse phase generator, but also in the fine rotator sectioncomposed of a cascade of single-bit interpolators. As a diagram of finerotator states in FIG. 6 shows, the code employed by the fine rotator isGray, meaning that the neighbor states are different in only one controlbit which already minimizes the risk of glitching significantly.Nevertheless use of an additional intermediate step during the switchingof a single-bit interpolation section, particularly for thehighest-weight (MSB) section provides additional protection against edgedistortions during code transitions.

Let us consider the structure of a single-bit fine interpolation rotatorstage in more detail. While on block diagram such stage is composed oftwo different devices, a 2:1 multiplexer (with feed-throughcompensation) and a 1:1 interpolator, in actual implantation both ofthese devices are made of identical parts, specifically, each is made ofa pair of slew-rate-limited 2:1 multiplexers with internal feed-throughcompensation, as it is shown in FIG. 14. Within each pair of thesemultiplexers the inputs and outputs are shared, while select controlsare separate. One pair serves as a permanent 1:1 interpolator for theodd phase output and so the select bits of its two multiplexers arepermanently wired to two opposite values, so one instance of themultiplexer drives the output with the first input, while the otherdrives it with the second input yielding 1:1 interpolation action. Thepair that serves as a multiplexer of the two input clock phases (labeledeven and odd) is controlled similarly to the interpolating multiplexeswithin the merging delay lines described earlier, i.e. the select inputsof its two multiplexers are driven with the “early” and “late” copies ofthe select signals. An important advantage of using identical parts toimplement the multiplexer and the 1:1 interpolator of the single-bitinterpolation section is that it guarantees equal propagation delays forthe signals forming its even and odd outputs, which benefitssignificantly the rotator accuracy.

FIG. 15 shows a method 1500 for programmable delay generation of equaldelay steps, in accordance with an embodiment of the present principles.The phase rotation is implemented using signals having full rail-to-railswing.

At step 1510, a first delay line is formed having a plurality of stages.Each of the plurality of stages includes a respective delay buffer andhaving one signal input and one signal output.

At step 1520, a second delay line is formed having a plurality of stagesequal in number to the plurality of stages of the first delay line. Eachof the plurality of stages of the second delay line includes arespective selecting element and has two signal inputs, one select inputfor selecting one of the two signal inputs, and one signal output. Thefirst delay line and the second delay line are configured in parallelwith respect to each other, are interconnected, and have a same signalpropagation direction. The delay steps provided by each of the pluralityof stages of the second delay line is equal to a difference between adelay through one of the plurality of stages of the first delay line anda delay through one of the plurality of stages of the second delay line.

FIG. 16 shows a method 1600 for cascaded interpolation, in accordancewith an embodiment of the present principles.

At step 1610, a plurality of single-bit interpolator stages is formed.Each of the stages has a 2:1 multiplexer and a 1:1 interpolator. The 2:1multiplexer and the 1:1 interpolator each receive two input signalshaving two different phases. The 2:1 multiplexer is configured to outputone of the two input signals based on a select input. The 1:1interpolator is configured to output an interpolated signal having aphase at a mid-point between the two different phases.

At step 1620, a phase converter is formed connected to a last stage ofthe plurality of single-bit interpolator stages. The phase converter isconfigured to convert the interpolated signal output from the 1:1interpolator of the last stage and the one of the two input signalsoutput from the 2:1 multiplexer of the last stage into a single finaloutput signal of a given phase.

Having described preferred embodiments of a system and method (which areintended to be illustrative and not limiting), it is noted thatmodifications and variations can be made by persons skilled in the artin light of the above teachings. It is therefore to be understood thatchanges may be made in the particular embodiments disclosed which arewithin the scope of the invention as outlined by the appended claims.Having thus described aspects of the invention, with the details andparticularity required by the patent laws, what is claimed and desiredprotected by Letters Patent is set forth in the appended claims.

What is claimed is:
 1. A programmable delay generator of equal delaysteps, comprising: a first delay line having a plurality of stages, eachof the plurality of stages including a respective delay buffer andhaving one signal input and one signal output; and a second delay linehaving a plurality of stages equal in number to the plurality of stagesof the first delay line, each of the plurality of stages of the seconddelay line including a respective selecting element and having twosignal inputs, one select input for selecting one of the two signalinputs, and one signal output, wherein the first delay line and thesecond delay line are configured in parallel with respect to each other,are interconnected, and have a same signal stage propagation order, andwherein each of the delay steps provided by each of the plurality ofstages of the second delay line is equal to a difference between a delaythrough one of the plurality of stages of the first delay line and adelay through one of the plurality of stages of the second delay line.2. The programmable delay generator of claim 1, wherein the one signaloutput of each of the plurality of stages of the first delay line excepta last one of the plurality of stages is respectively connected to theone signal input of a next one of the plurality of stages of the firstdelay line and to one of the two signal inputs of a corresponding one ofthe plurality of stages of the second delay line.
 3. The programmabledelay generator of claim 2, wherein the input clock signal is receivedby a first one of the plurality of stages of the first delay line and issequentially propagated to each of the following ones of the pluralityof stages of the first delay line until the last one.
 4. Theprogrammable delay generator of claim 3, wherein the one signal outputof each of the plurality of stages of the second delay line isrespectively connected to one of the two signal inputs of a next one ofthe plurality of stages of the second delay line, and wherein a last oneof the plurality of stages of the second delay line forms an output ofthe programmable delay generator.
 5. The programmable delay generator ofclaim 1, wherein a propagation path for the input clock signal isconfigured such that the input clock signal propagates through theplurality of stages of the first delay line and also propagates througha respective activated tap formed from the one signal output of a givenone of the plurality of stages of the first delay line to a given one ofthe two inputs of a given one of the plurality of stages of the seconddelay line and following ones of the plurality of stages of the seconddelay line.
 6. The programmable delay generator of claim 1, whereindifferent propagation delays for the input clock signal are obtained byactivating different taps of the first delay line, wherein each of thedifferent taps is respectively formed from the one signal output of arespective one the plurality of stages of the first delay line.
 7. Theprogrammable delay generator of claim 6, further comprising one or moreadditional delay lines, each having a same configuration as the seconddelay line, wherein a respective output of the second delay line formedfrom the one signal output of a last one of the plurality of stages ofthe second delay line provides a first delayed output signal from theprogrammable delay generator, and wherein the one or more additionaldelay lines provide additional delayed output signals each havingdifferent delays.
 8. The programmable delay generator of claim 7,wherein each of the second delay line and the one or more additionaldelay lines respectively comprise a set of taps connected to the firstdelay line, and the different delays are obtained by activatingdifferent ones of the taps.
 9. The programmable delay generator of claim6, further comprising a plurality of polarity switches, each of theplurality of polarity switches being connected in between a respectiveone of the different taps of the first delay line and a respective oneof corresponding merging taps of the second delay line, and isconfigured to provide a desired polarity to the input clock signalbefore the input clock signal propagates through the second delay line.10. The programmable delay generator of claim 1, wherein theprogrammable delay generator is comprised within a coarse phasegeneration stage of a two-stage phase rotator.
 11. The programmabledelay generator of claim 1, wherein each of the plurality of stages ofthe second delay line further includes a respective delay buffer coupledto an output of the respective switching element.
 12. The programmabledelay generator of claim 1, wherein the respective switching elementcomprises a 2:1 multiplexer.
 13. The programmable delay generator ofclaim 1, wherein the first delay line and the second delay line areconfigured to generate full-swing signals.
 14. A method for programmabledelay generation of equal delay steps, comprising: forming a first delayline having a plurality of stages, each of the plurality of stagesincluding a respective delay buffer and having one signal input and onesignal output; and forming a second delay line having a plurality ofstages equal in number to the plurality of stages of the first delayline, each of the plurality of stages of the second delay line includinga respective selecting element and having two signal inputs, one selectinput for selecting one of the two signal inputs, and one signal output,wherein the first delay line and the second delay line are configured inparallel with respect to each other are interconnected and have a samesignal stage propagation order, and wherein each of the delay stepsprovided by each of the plurality of stages of the second delay line isequal to a difference between a delay through one of the plurality ofstages of the first delay line and a delay through one of the pluralityof stages of the second delay line.
 15. The method of claim 14, furthercomprising configuring a propagation path for the input clock signalsuch that the input clock signal propagates through each of theplurality of stages of the first delay line and also propagates througha respective activated tap formed from the one signal output of a givenone of the plurality of stages of the first delay line to a given one ofthe two inputs of a given one of the plurality of stages of the seconddelay line and following ones of the plurality of stages of the seconddelay line.
 16. The method of claim 14, wherein the first delay line andthe second delay line are configured to generate full-swing signals.